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1 ? fn7297.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners. EL7564 monolithic 4 amp dc:dc step-down regulator the EL7564 is an integrated, full- featured synchronous step-down regulator with output voltage adjustable from 1.0v to 3.8v. it is capable of delivering 4a continuous current at up to 95% efficiency. the EL7564 operates at a constant frequency pulse width modulation (pwm) mode, making external synchronization possible. patented on-chip resistorle ss current sensing enables current mode control, which pr ovides cycle-by-cycle current limiting, over-current protection, and excellent step load response. the EL7564 features power tracking, which makes the start-up sequencing of multiple converters possible. a junction temperature indicator conveniently monitors the silicon die tem perature, saving the designer time on the tedious thermal characterization. the minimal external components and full functionality make this EL7564 ideal for desktop and portable applications. the EL7564 is specified for operation over the -40c to +85c temperature range. typical application diagrams EL7564 [20-pin so (0.300?)] top view features ? integrated synchronous mosfets and current mode controller ? 4a continuous output current ? up to 95% efficiency ? 4.5v to 5.5v input voltage ? adjustable output from 1v to 3.8v ? cycle-by-cycle current limit ? precision reference ? 0.5% load and line regulation ? adjustable switching frequency to 1mhz ? oscillator synchronization possible ? internal soft start ? over voltage protection ? junction temperature indicator ? over temperature protection ? under voltage lockout ? multiple supply start-up tracking ? power good indicator ? 20-pin so (0.300?) package ? 28-pin htssop package applications ? dsp, cpu core and io supplies ? logic/bus supplies ? portable equipment ? dc:dc converter modules ? gtl + bus power supply manufactured under u.s. patent no. 5,7323,974 typical application diagrams continued on page 3 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 0.1f 390pf 0.22f 22 ? 2.2nf 330f v in 5v v out 3.3v, 4a 2.37k ? 1k ? 330f 0.22f 4.7h vref sgnd cosc vdd vtj pgnd pgnd vin stp stn en fb pg vdrv vhi lx lx pgnd pgnd pgnd 100pf c5 c4 r4 c3 c2 c1 c6 d1 l1 c7 r2 c10 r1 ordering information part number package tape & reel pkg. no. EL7564cm 20-pin so (0.300?) - mdp0027 EL7564cm-t13 20-pin so (0.300?) 13? mdp0027 EL7564cre 28-pin htssop - mdp0048 EL7564cre-t13 28-pin htssop 13? mdp0048 data sheet may 9, 2003
2 absolute maxi mum ratings (t a = 25c) supply voltage between v in or v dd and gnd . . . . . . . . . . . . +6.5v v lx voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in +0.3v input voltage . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v, v dd +0.3v v hi voltage . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v, v lx +6.5v storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . +135 caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v dd = v in = 5v, t a = t j = 25c, c osc = 1.2nf, unless otherwise specified. parameter description conditions min typ max unit v ref reference accuracy 1.24 1.26 1.28 v v reftc reference temperature coefficient 50 ppm/c v refload reference load regulation 0 < i ref < 50a -1 % v ramp oscillator ramp amplitude 1.15 v i osc_chg oscillator charge current 0.1v < v osc < 1.25v 200 a i osc_dis oscillator discharge current 0.1v < v osc < 1.25v 8 ma i vdd +v drv v dd +v drv supply current v en = 4v, f osc = 120khz 2 3.5 5 ma ivdd_off v dd standby current en = 0 1 1.5 ma v dd_off v dd for shutdown 3.5 3.9 v v dd_on v dd for startup 44.35v t ot over temperature threshold 135 c t hys over temperature hysteresis 20 c i leak internal fet leakage current en = 0, l x = 5v (low fet), l x = 0v (high fet) 10 a i lmax peak current limit 5 a r dson fet on resistance wafer level test only 30 60 m ? r dsontc r dson te m p c o 0.2 m ? /c i stp auxiliary supply tracking positive input pull down current v stp = v in / 2 -4 2.5 a i stn auxiliary supply tracking negative input pull up current v stn = v in / 2 2.5 4 a v pgp positive power good threshold with respect to target output voltage 6 14 % v pgn negative power good threshold with respect to target output voltage -14 -6 % v pg_hi power good drive high i pg = +1ma 4 v v pg_lo power good drive low i pg = -1ma 0.5 v v ovp over voltage protection 10 % v fb output initial accuracy (EL7564cm) i load = 0a 0.960 0.975 0.99 v output initial accuracy (EL7564cre) 0.977 0.992 1.007 v v fb_line output line regulation v in = 5v, ? v in = 10%, i load = 0a 0.5 % v fb_load output load regulation 0.5a < i load < 4a 0.5 % v fb_tc output temperature stability -40c < t a < 85c, i load = 2a 1 % i fb feedback input pull up current v fb = 0v 100 200 na v en_hi en input high level 3.2 4 v v en_lo en input low level 1 v i en enable pull up current v en = 0 -4 -2.5 a EL7564
3 typical application diagrams (continued) el7654 (28-pin htssop) top view closed-loop ac electrical specifications v s = v in = 5v, t a = t j = 25c, c osc = 1.2nf, unless otherwise specified. parameter description conditions min typ max unit f osc oscillator initial accuracy 105 117 130 khz t sync minimum oscillator sync width 25 ns m ss soft start slope 0.5 v/ms t brm fet break before make delay 15 ns t leb high side fet minimum on time 150 ns d max maximum duty cycle 95 % 1 2 3 4 16 15 14 13 5 6 7 12 11 9 8 10 20 19 18 17 24 23 22 21 28 27 26 25 0.22f 22 ? 2.2nf v in 5v v out 3.3v, 4a 2.37k ? 1k ? 330f 0.22f 4.7h vref sgnd cosc vdd vtj pgnd pgnd pgnd pgnd vin en fb pg vdrv vhi lx lx lx lx lx 100pf r4 c3 c2 c6 d1 l1 c7 r2 c10 r1 vin nc stp stn lx nc pgnd pgnd 0.1f 390pf c5 c4 330f EL7564
4 pin descriptions 20-pin so (0.300?) 28-pin htssop pin name pin function 1 1 vref bandgap reference bypass capacitor; typically 0.1f to sgnd 2 2 sgnd control circuit negative supply or signal ground 3 3 cosc oscillator timing capa citor (see performance curves) 4 4 vdd control circuit positive supply; norma lly connected to vin through an rc filter 5 5 vtj junction temperature monitor; connected with 2.2nf to 3.3nf to sgnd 6, 7 6, 7, 8, 9 pgnd ground return of the regulator; connec ted to the source of the low-side synchronous nmos power fet 8 10, 11 vin power supply input of the regulator; c onnected to the drain of the high-side nmos power fet 9 13 stp auxiliary supply tra cking positive input; tied to regulator output to synchronize start up with a second supply; leave open for stand alone operation; 2a internal pull down current 10 14 stn auxiliary supply tracking negative input; connec t to output of a second supply to synchronize start up; leave open for stand alone operation; 2a internal pull up current 11, 12, 13 15, 16 pgnd ground return of the regulator; connec ted to the source of the low-side synchronous nmos power fet 14, 15 18, 19, 20, 21, 22, 23 lx inductor drive pin; high current output whose average voltage equals the regulator output voltage 16 24 vhi positive supply of high-si de driver; boot strapped from vdrv to lx with an external 0.22f capacitor 17 25 vdrv positive supply of low-side driv er and input voltage for high side boot strap 18 26 pg power good window comparator output; logic 1 when regulator output is within 10% of target output voltage 19 27 fb voltage feedback input; connected to exter nal resistor divider between vout and sgnd; a 125na pull-up current forces vout to sgnd in the event that fb is floating 20 28 en chip enable, active high; a 2a internal pull up current enables t he device if the pin is left open; a capacitor can be added at this pin to delay the start of converter typical performance curves figure 1. EL7564cm efficiency figure 2. EL7564cre efficiency v in =5v 100 60 65 70 75 85 95 04 3.5 3 2.5 2 1 0.5 1.5 load current i o (a) efficiency (%) v o =3.3v v o =1.8v 80 90 v o =2.8v v in =5v 100 95 90 85 80 75 70 65 60 0.1 0.6 1.1 1.6 2.1 2.6 3.1 3.6 4.1 i o (a) efficiency (%) v o =3.3v v o =1.8v v o =2.5v EL7564
5 figure 3. EL7564cm total converter power loss fi gure 4. EL7564cre total converter power loss figure 5. EL7564cm load regulation fi gure 6. EL7564cre load regulation figure 7. EL7564cm ja vs copper area figure 8. EL7564cre thermal resistance vs pcb area - no airflow typical performance curves (continued) v in =5v 2 0 power loss (w) 0.4 0.8 1.2 1.6 04 3.5 3 2.5 2 1 0.5 1.5 output current i o (a) v o =3.3v v o =1.8v v o =2.8v 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 00.511.522.533.54 i o (a) p loss (w) v o =3.3v v o =1.8v 0.2 0.5 4 3.5 3 2.5 1.5 12 load current i o (a) v o =3.3v 3.275 output voltage (v) 3.285 3.295 3.305 3.315 3.325 v in =5v v in =5.5v v in =4.5v v o =3.3v 1.5 1 0.5 0 -0.5 -1 -1.5 01234 i o (a) v o (v) (%) v in =4.5v v in =5v v in =5.5v test condition: chip in the center of copper area 50 30 46 42 38 34 14 1.5 2.5 3.5 pcb copper heat-sinking area (in 2 ) thermal resistance (c/w) 23 with no airflow with 100 lfpm airflow 1 oz. copper pcb used condition: EL7564re thermal pad soldered to 2-layer pcb with 0.039? thickness and 1 oz. copper on both sides 50 45 40 35 30 25 11.5 33.54 pcb area (in 2 ) ja (c/w) 22.5 EL7564
6 figure 9. oscillator frequency vs temper ature figure 10. switching frequency vs c osc figure 11. current limit vs t j figure 12. vtj vs junction temperature figure 13. v ref vs die temperature figure 14. switching waveforms typical performance curves (continued) 360 280 350 340 330 320 310 290 -40 80 -20 204060 temperature (c) oscillator frequency (khz) 0 300 i o =0a i o =4a 1000 100 900 800 700 500 300 200 100 1000 200 400 600 800 c osc (pf) f s (khz) 900 300 500 700 600 400 8 3 7 6 5 4 -40 120 -20 40 100 t j (c) i lmt (a) 080 60 20 v in =4.5v v in =5.5v v in =5v 1.5 0.9 1.3 1.1 0150 25 junction temperature (c) vtj 125 50 75 100 1.27 1.256 1.268 1.266 1.264 1.262 1.26 1.258 -50 150 -10 30 70 110 die temperature (c) v ref (v) v in =5v, v o =3.3v, i o =4a ? v in v lx i l ? v o EL7564
7 figure 15. transient response figure 16. power-up figure 17. power-down figure 18. releasing en figure 19. shut-down figure 20. short-circuit protection typical performance curves (continued) v in =5v, v o =3.3v, i o =0.2a-4a i o ? v o v in =5v, v o =3.3v, i o =2a v in v o v in =5v, v o =3.3v, i o =4a v in v o v in =5v, v o =3.3v, i o =2a en v o v in =5v, v o =3.3v, i o =4a en v o v in =5v i o v o EL7564
8 block diagram figure 21. package power dissipation vs ambient temperature figure 22. package power dissipation vs ambient temperature typical performance curves (continued) jedec jesd51-7 high effective thermal conductivity test boar d. htssop exposed diepad soldered to pcb per jesd51-5 3.5 3 2.5 1.5 1 0.5 0 0 255075100 150 ambient temperature (c) power dissipation (w) 3.333w j a = 3 0 c/ w ht s s o p 2 8 125 85 2 jedec jesd51-3 low effective thermal conductivity test board 1 0.9 0.6 0.4 0.3 0.2 0.1 0 0 25 50 75 100 150 ambient temperature (c) power dissipation (w) 85 0.8 0.5 0.7 125 909mw j a = 1 1 0 c / w h t s s o p 2 8 drivers pwm controller power tracking current sense voltage reference oscillator 2.2nf 0.22f 22 ? stp stn controller supply sgnd power power fet fet 390pf 0.1f 0.22f 4.7h v out 2370 ? 1k ? 330f v ref c osc v hi v in pgnd v dd v tj v drv fb d 1 en - + pg v ref 100pf junction temperature EL7564
9 applications information circuit description general the EL7564 is a fixed frequency, current mode controlled dc:dc converter with integrated n-channel power mosfets and a high precision reference. the device incorporates all the active circuitry required to implement a cost effective, user-programmable 4a synchronous step- down regulator suitable for use in dsp core power supplies. by combining fused-lead packaging technology with an efficient synchronous switching architecture, high power output (13w) can be realized without the use of discrete external heat sinks. theory of operation the EL7564 is composed of seven major blocks: 1. pwm controller 2. nmos power fets and drive circuitry 3. bandgap reference 4. oscillator 5. temperature sensor 6. power good and power on reset 7. auxiliary supply tracking pwm controller the EL7564 regulates output voltage through the use of current-mode controlled pulse width modulation. the three main elements in a pwm controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modul ator output. in a step-down (buck) converter, the feedback loop forces the time- averaged output of the modulato r to equal the desired output voltage. unlike pure voltage-mode control systems, current- mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. the voltage loop minimizes dc and transient errors in the output voltage by adjusting the pwm duty-cycle in response to changes in line or load conditions. since the output voltage is equal to the time-averaged of the modulator output, the relatively large lc time constant found in power supply applications generally results in low bandwidth and poor transient response. by directly monitoring changes in inductor current via a series se nse resistor the controller's response time is not entirely limited by the output lc filter and can react more quickly to changes in line and load conditions. this feed-forward characteristic also simplifies ac loop compensation since it adds a zero to the overall loop response. through proper selection of the current- feedback to voltage-feedback ratio the overall loop response will approach a one-pole system. the resulting system offers several advantages over traditi onal voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. the heart of the controller is an input direct summing comparator which sum voltage feedback, current feedback, slope compensation ramp and power tracking signals together. slope compensation is required to prevent system instability that occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. the slope compensation is fixed internally and optimized for 500ma inductor ripple current. the power tracking will not contribute any input to the comparator st eady-state operation. current feedback is measured by the pa tented sensing scheme that senses the inductor current flowing through the high-side switch whenever it is conduc ting. at the beginning of each oscillator period the high-side nmos switch is turned on. the comparator inputs are gated off for a minimum period of time of about 150ns (leb) after the high-side switch is turned on to allow the system to settle. the leading edge blanking (leb) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. if the inductor current exceed s the maximum current limit (i lmax ) a secondary over-current comparator will terminate the high-side switch on time. if i lmax has not been reached, the feedback voltage fb deriv ed from the regulator output voltage v out is then compared to the internal feedback reference voltage. the resultant error voltage is summed with the current feedback an d slope compensation ramp. the high-side switch remains on until all four comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. however, the maximum on-duty ra tio of the high-side switch is limited to 95%. in order to eliminate cross-conduction of the high-side and low-side switches a 15ns break-before- make delay is incorporated in the switch drive circuitry. the output enable (en) input allows the regulator output to be disabled by an external logic control signal. output voltage setting in general, EL7564cm: and EL7564cre: a 100na pull-up current from fb to v dd forces v out to gnd in the event that fb is floating. v out 0.975v 1 r 2 r 1 ------ - + ?? ?? ?? = v out 0.992v 1 r 2 r 1 ------ - + ?? ?? ?? = EL7564
10 nmos power fets and drive circuitry the EL7564 integrates low on-resistance (30m ? ) nmos fets to achieve high efficien cy at 4a. in order to use an nmos switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (l x ). this is accomplished by bootstrapping the v hi pin above the l x voltage with an external capacitor c vhi and internal switch and diode. when the low-side switch is turned on and the l x voltage is close to gnd potential, capacitor c vhi is charged through an internal switch to v drv , typically 5v. at the beginning of the next cycle the high-side switch turns on and the l x pins begin to rise from gnd to v in potential. as the l x pin rises the positive plate of capacitor c vhi follows and eventually reaches a value of v drv + v in , typically 10v, for v drv = v in = 5v. this voltage is then level shifted and used to drive the gate of the high-side fet, via the v hi pin. a value of 0.22f for c vhi is recommended. reference a 1.5% temperature compensated bandgap reference is integrated in the EL7564. the external v ref capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. a value of 0.1f is recommended. oscillator the system clock is generated by an internal relaxation oscillator with a ma ximum duty-cycle of approximately 95%. operating frequency can be adjusted through c osc . when external synchronization is required, always choose c osc such that the free-running frequency is at least 20% lower than that of the sync source to accommodate component and temperature variations. figure 21 shows a typical connection. junction temperature sensor an internal temperature sens or continuously monitors die temperature. in the event that the die temperature exceeds the thermal trip-point, the system is in a fault state and will be shut down. the upper and low trip-points are set to 135c and 115c respectively. the v tj pin is an accurate indication of the internal silicon junction temperature (see performance curve.) the junction temperature t j (c) can be determined from the following relation: where v tj is the voltage at the v tj pin in volts. power good and power on reset during power up the output regulator will be disabled until v in reaches a value of approximately 4v. about 500mv hysteresis is present to elim inate noise-induced oscillations. under-voltage and over-voltage conditions on the regulator output are detected through an internal window comparator. a logic high on the pg output indicates that the regulated output voltage is within about +10% of the nominal selected t j 75 1.2 vtj ? 0.00384 ------------------------- + = 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 EL7564 1 20 external oscillator bat54s 100pf 390pf figure 23. oscillator synchronization EL7564
11 power tracking the power tracking pins stp and stn are the inputs to a comparator, whose hi output forces the pwm controller to skip switching cycles. 1. linear tracking in this application, it is always the case that the lower voltage supply v c tracks the higher output supply v p . please see figure 22 below. figure 24. linear power tracking 1 2 15 14 13 12 6 7 8 11 10 9 20 19 EL7564 - + 1 2 15 14 13 12 6 7 8 11 10 9 20 19 EL7564 - + v c v p v out time v c v p EL7564
12 2. offset tracking the intended start-up sequence is shown in figure 23a. in this configuration, v c will not start until v p reaches a preset value of: r b r a r b + ---------------------- v in figure 25. offset power tracking v out time v c v p 1 2 15 14 13 12 6 7 8 11 10 9 20 19 EL7564 - + 1 2 15 14 13 12 6 7 8 11 10 9 20 19 EL7564 - + v c v p stp stn stp stn v in r a r b EL7564
13 the second way of offset tracking is to use the en and power good pins, as shown in figure 24. in this configuration, v p does not have to be larger than v c . 3. external soft start an external soft start can be combined with auxiliary supply tracking to provide desired soft start other than internally preset soft start (figure 25). the appropriate start-up time is: t s rc v o v in --------- = figure 26. offset tracking v c 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 EL7564 2 3 16 15 14 13 5 6 7 12 11 9 8 10 19 18 EL7564 1 20 1 20 v p en pg en pg time v c v p 1 2 15 14 13 12 6 7 8 11 10 9 20 19 EL7564 - + v out stp stn v in r c figure 27. external soft start EL7564
14 4. start-up delay a capacitor can be added to the en pin to delay the converter start-up (figure 26) by utilizing the pull-up current. the delay time is approximately: thermal management the EL7564cm utilizes ?fused lead? packaging technology in conjunction with the system boar d layout to ac hieve a lower thermal resistance than typically found in standard so20 packages. by fusing (or connecting) multiple external leads to the die substrate within the package, a very conductive heat path is created to the outside of the package. this conductive heat path must then be connected to a heat sinking area on the pcb in order to dissipate heat out and away from the device. the conductive paths for the EL7564cm package are the fused leads: # 6, 7, 11, 12, and 13. if a sufficient amount of pc b metal area is connected to the fused package leads, a junction-to-ambient resistance of 43c/w can be achieved (compared to 85c/w for a standard so20 package). the general relationship between pcb heat-sinking metal area and the thermal resistance for this package is shown in the performance curves section of this data sheet. it can be readily seen that the thermal resistance for this package approaches an asymptotic value of approximately 43c/w without any airflow, and 33c/w with 100 lfpm airflow. additional information can be found in application note #8 (measuring the thermal resistance of power surface-mount packages). for a thermal shutdown die junction temperature of 135c, and power dissipation of 1.5w, the ambient temperatur e can be as high as 70c without airflow. with 100 lfpm airflow, the ambient temperature can be extended to 85c. the EL7564cre utilizes the 28-pin htssop package. the majority of heat is dissipated through the heat pad exposed at the bottom of the package. therefore, the heat pad needs to be soldered to the pcb. the thermal resistance for this package is as low as 29c/w, better than that of so20. typical performance is shown in the curves section. the actual junction temperature can be measured at v tj pin. since the thermal performanc e of the ic is heavily dependent on the board layout, the system designer should exercise care during the design phase to ensure that the ic will operate under the worst-case environmental conditions. layout considerations the layout is very important for the converter to function properly. power ground ( ) and signal ground ( ) should be separated to ensure that the high pulse current in the power ground never interferes with the sensitive signals connected to signal ground. they should only be connected at one point (normally at the negative side of either the input or output capacitor.) the trace connected to the fb pin is the most sensitive trace. it needs to be as short as possible and in a ?quiet? place, preferably with the pgnd or sgnd traces surrounding it. in addition, the bypass capacitor connected to the v dd pin needs to be as close to the pin as possible. the heat of the chip is mainly dissipated through the pgnd pins for the cm package, and through the heat pad at the bottom for the cre package. maximizing the copper area around these pgnd pins or the heat pad is preferable. in addition, a solid ground plane is always helpful for the emi performance. the demo board is a good exampl e of layout based on these principles. please refer to the EL7564 application brief for the layout. t d ms () 1200 c f () = figure 28. start-up delay 1 2 15 14 13 12 6 7 8 11 10 9 20 19 EL7564 - + v out stp stn c time v o v in t d EL7564
15 package outline drawing - 20-pin so (0.300?) package note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at EL7564
16 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com package outline drawing (28-pin htssop package) note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at EL7564

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